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RC96V24DP single device data/fax modem data pump the rockwell RC96V24DP is a low power, v.22 bis 2400 bps data/fax modem data pump in a single vlsi package. the rc2324dpl is identical to the RC96V24DP except fax modes are not provided. in this document, all references to the RC96V24DP also apply to the rc2324dpl except for the fax modes and as otherwise noted. the modem operates over the public switched telephone network (pstn), as well as on point-to-point leased lines. the modem supports data modes meeting the requirements specified in ccitt recommendations v.22 bis, v.22, v.23, and v.21, as well as bell 212a and bell 103. the modem supports fax modes meeting the requirements specified in ccitt v.29, v.27 ter, and v.21 channel 2 synchronous. internal hdlc support eliminates the need for an external serial input/output (sio) device or comparable functions in the host controller in products incorporating error correction and t.30 protocols. the modem includes two cmos vlsi functions C a digital signal processor (dsp) and an integrated analog function (ia). the RC96V24DP integrates these functions into a single 68-pin plastic leaded chip carrier (plcc). detailed hardware and software interface information is described in the designer's guide (order no. 822). functional block diagram RC96V24DP modem device telephone line interface speaker amplifier (optional) eye pattern generator (optional) host parallel bus interface (17) serial interface (5) 2 2 4 product features ? single cmos vlsi device ? low power requirements C single voltage: + 5 vdc 5% C operating: 300 mw (typical) C sleep: 15 mw (typical) ? 2-wire operation C full- duplex (fdx) for data modes C half-duplex (hdx) for fax modes ? data configurations: C v.22 bis, v.22, v.23, v.21 C bell 212a, bell 103 ? fax configurations (RC96V24DP): C v.29, v.27 ter, v.21 channel 2 ? voice mode ? dtmf detection ? receive dynamic range: -9 dbm to -43 dbm ? transmit level: -10 dbm 1 db using internal hybrid circuit; attentuation selectable in 1 db steps ? multi-mode data/fax detection support ? v.22 bis fallback/fall-forward -2400/1200 bps ? serial data: synchronous and asynchronous ? parallel data: synchronous (including hdlc) and asynchronous ? programmable ring detect ? programmable dialer ? programmable tone detect bandpass filters ? adjustable speaker output to monitor received signal ? diagnostics ? host bus interface memory for configuration, control, and parallel data; 8086 microprocessor bus compatible ? 5-pin serial data interface; ttl compatible ? equalization C adaptive equalizer in receiver C selectable and programmable fixed compromise equalizers in both receiver and transmitter ? loopback configurations C local analog, local digital, and remote digital ? answer and originate handshake in data modes ? training sequences for fax modes ? leased line operation d96v24dsa
copyright ? 1998 rockwell semiconductor systems, inc. all rights reserved. print date: september 1998 rockwell semiconductor systems, inc. reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. information furnished is believed to be accurate and reliable. however, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result fr om its use. no license is granted by its implication or otherwise under any patent or intellectual property rights of rockwell semiconductor systems, inc. rockwell semiconductor systems, inc. products are not designed or intended for use in life support appliances, devices, or syst ems where malfunction of a rockwell semiconductor systems, inc. product can reasonably be expected to result in personal injury or death. rockwell semiconductor systems, inc. customers using or selling rockwell semiconductor systems, inc. products for use in such applications do so at their own risk and agree to fully indemnify rockwell semiconductor systems, inc. for any damages resulting from such improper use or sale. specifications are subject to change without notice. printed in the united states of america ordering information note: rc2324dpl does not support fax capabilities. rc9624dp does not support voice. marketing number manufacturing number package RC96V24DP r6653-12 68 pin plcc RC96V24DP r6653-17 100 pin pqfp rc9624dp r6653-16 68 pin plcc rc9624dp r6653-21 100 pin pqfp rc2324dpl r6653-15 68 pin plcc rc2324dpl r6653-20 100 pin pqfp
1-1 d96v24dsa 1.0 functional description 1.1 overview the rockwell RC96V24DP is a low power, v.22 bis 2400 bps data/fax modem data pump in a single vlsi package. 1.2 technical specifications 1.2.1 configurations and rates the selectable modem configurations, along with the corresponding signaling (baud) rates and data rates, are listed in table 1-1 (conf bits). note: bit names refer to control or status bits in dsp interface memory which are set or reset by the host processor (see table 3-1 and table 3-2). 1.2.2 data encoding the data encoding conforms to ccitt recommendations v.29, v.27 ter, v.22 bis, v.22, v.23, or v.21, or to bell 212a or 103, depending on the selected configuration. 1.2.3 tone generation answer tone: a ccitt (2100 15 hz) or bell (2225 10 hz) answer tone can be generated. guard tone: a1800 20 hz guard tone can be generated (enabled by the gte bit). dtmf tones: dual tone multi-frequency (dtmf) tones can be generated with a frequency accuracy of 1.5%. user defined tones: a user-defined single or dual tone can be generated from 200 hz to 3000 hz 5 hz.
1.0 functional description RC96V24DP 1.2 technical specifications single device data/modem data pump 1-2 d96v24dsa 1.2.4 tone detection answer tone and call progress tones: tones can be detected as follows: ? call progress frequency range: 340 5 hz to 640 5h z ? answer tone frequency ranges: ccitt (2100 15hz), bell (2225 10 hz), or bell fsk originate tone (1270 10 hz) ? detection range: -9 dbm to -43 dbm ? default detection threshold: -43 dbm ? response time: 75 2 ms ? the passband and tone detect threshold can be changed in dsp ram. v.23 and v21 tones: tones can be detected as follows: ? v.23 forward channel mark: 1300 10 hz ? v.23 backward channel mark: 390 10 hz ? v.21 high band mark (1650 10 hz) or low band mark (980 10 hz) ? detection range: -9 dbm to -43 dbm ? default detection threshold: -43 dbm ? response time: 25 2 ms the passbands and tone detect thresholds can also be changed in the dsp ram. 1.2.4.1 dtmf detection the modem can detect a valid dtmf tone pair (indicated by dtdet) and load a corresponding hexadecimal code into the modem interface memory (dtdig). 1.2.4.2 equalizers equalization functions are incorporated that improve performance when operating over low quality lines. automatic adaptive equalizer. an automatic adaptive equalizer in the receiver compensates for transmission line amplitude and group delay distortion. updating of the taps can be enabled or disabled (eqfz bit). the equalizer taps can also be reset (eqres bit). fixed compromise equalizers. fixed compromise equalizers are provided in the transmitter and receiver. the equalizers are programmable in dsp ram. 1.2.4.3 transmit level the transmitter output level is -10 dbm 1 db using the internal hybrid circuit. the attentuation is selectable from 0 dbm to -15 dbm in 1 db steps (tlvl bits). 1.2.4.4 transmit timing transmitter timing is selectable between internal (0.01%), external, or loopback (txclk bits). when external clock is selected, the external clock rate must equal the desired data rate 0.01% with a duty cycle of 50 20%. 1.2.4.5 scrambler/ descrambler the modem incorporates a self-synchronizing scrambler/descrambler satisfying the applicable ccitt or bell requirement. the scrambler and descrambler can be enabled or disabled (sdis and ddis bits, respectively).
RC96V24DP 1.0 functional description single device data/modem data pump 1.2 technical specifications d96v24dsa 1-3 1.2.4.6 receive level the receiver satisfies performance requirements for a received line signal from -9 dbm to -43 dbm. the default rlsd turn-on and rlsd turn-off thresholds are -43 dbm and -48 dbm, respectively. the rlsd threshold levels are programmable in dsp ram. 1.2.4.7 receiver timing the modem can track a frequency error up to 0.03% in the associated transmit timing source. 1.2.4.8 carrier recovery the modem can track a frequency offset up to 7 hz in the received carrier with less than a 0.2 db degradation in bit error rate (ber).
1.0 functional description RC96V24DP 1.2 technical specifications single device data/modem data pump 1-4 d96v24dsa table 1-1. configurations, signaling and data rates configuration modulation transmitter carrier frequency (hz) 0.01% data rate (bps) baud bits per constella- tion sample rate answer 2 originate 2 0.01% (symbols/ sec) symbol points (samples/ sec) data modes v.22 bis qam 2400 1200 2400 3 600 4 16 7200 v.22 dpsk 2400 2400 1200 1200 1200 3 600 3 600 600 2 1 4 2 7200 7200 bell 212a dpsk 2400 1200 1200 3 600 2 4 7200 bell 103 fsk 2225 m 2025 s 1270 m 1070 s 0-300 4 0-300 4 1 1 7200 v.21 fsk 1650 m 1850 s 980 m 1180 s 0-300 4 0-300 4 1 1 7500 v.23 forward channel 5 fsk 1300 m 2100 s 1300 m 2100 s 1200 1200 1 1 9600 5 v.23 backward channel 5 fsk 390 m 450 s 390 m 450 s 75 75 1 1 7200 fax modes 6 v.29 qam qam qam 1700 1700 1700 1700 1700 1700 9600 7200 4800 2400 2400 2400 4 3 2 16 8 4 9600 7200 9600 v.27 ter dpsk dpsk 1800 1800 1800 1800 4800 2400 1600 1200 3 2 8 4 9600 9600 v.21 channel 2 fsk 1650 m 1850 s 1650 m 1850 s 300 300 1 1 9600 dial/call progress mode 600 7200 tone generator/ tone detector mode 600 7200 notes: (1) modulation legend: qam quadrature amplitude modulation dpsk differential phase shift keying fsk frequency shift keying (2) m indicates a mark condition; s indicates a space condition. (3) synchronous accuracy = 0.01%; asynchronous accuracy = -2.5% to +1.0% (+2.3% if extended overspeed is selected). (4) value is upper limit for serial (e.g. 0-300). (5) rc2324dpl only. (6) RC96V24DP only. (7) 9600 samples per sec in v.23 fdx tx75/rx1200; 7200 samples per second in v.23 fdx tx1200/rx75.
RC96V24DP 1.0 functional description single device data/modem data pump 1.2 technical specifications d96v24dsa 1-5 1.2.4.9 rts-cts turn- on and turn-off sequences rts on to cts on and rts off to cts off response times are listed in table 1-3. in v.21, the transmitter turns off within 10 ms after rts goes off. for v.29, the turn-off sequence consists of approximately 5 ms of remaining data and scrambled ones followed by a 50 ms period of no transmitted energy. for v.27 ter, the turn-off sequence consists of approximately 7 ms of remaining data and scrambled ones at 1200 baud or approximately 7.5 ms of data and scrambled ones at 1600 baud followed by a 20 ms period of no transmitted energy. 1.2.5 serial or parallel interface the tpdm bit selects serial or parallel interface. serial interface. the five hardware lines (rxd, txd, tdclk, rdclk , and xtclk) are supported by four control and status bits in the interface memory (cts, dsr, rts, and rlsd). parallel interface. a 8086-compatible parallel microprocessor bus is supported. table 1-2. dial digits/tone pairs dial digit tone 1 (hz) tone 2 (hz) 1 697 1209 2 697 1336 3 697 1447 4 770 1209 5 770 1336 6 770 1447 7 852 1209 8 852 1336 9 852 1477 0 941 1336 * 941 1209 # 941 1477 spare b 967 1633
1.0 functional description RC96V24DP 1.2 technical specifications single device data/modem data pump 1-6 d96v24dsa 1.2.6 voice mode transmit voice. transmit voice samples can be sent to the modem digital-to- analog converter (dac) from the host through the transmit data buffer. receive voice. received voice samples from the modem analog-to-digital converter (adc) can be read by the host from the receive data buffer. 1.2.7 asynchronous conversion asynchronous mode is selected by the async bit. the asynchronous character format is 1 start bit, 5 to 8 data bits (wdsz bits), an optional parity bit (parsl and pen bits), and 1 or 2 stop bits (stb bit). valid character size, including all bits, is 7, 8, 9, 10 or 11 bits per character. signalling rate range. signalling rate range is selectable by the exos bit: ? basic range: +1% to -2.5% ? extended overspeed range: +2.3% to -2.5% break. break is handled as described in v.22 bis. table 1-3. rts-cts response times configuration turn on time turn off time data modes v.22 bis, v.22, and bell 212a (cc bit = 0) 2 ms 2 ms v.22 bis, v.22, and bell 212a (cc bit =1) 270 ms 2 ms v.21 and bell 103 2-5 ms 10 ms v.23 (RC96V24DP and rc2324dpl only) 11 ms 2 ms fax modes (RC96V24DP only) echo protector tone disabled (nv25 = 1) v.29 (all speeds) 253 ms 2 ms v.27 4800 898 ms 2 ms v.27 2400 1133 ms 9 ms v.21 20 ms 4 ms echo protector tone enabled (nv25 = 0) v.29 (all speeds) 253 ms 2 ms v.27 4800 1103 ms 2 ms v.27 2400 1338 ms 9 ms v.21 3095 ms 4 ms
RC96V24DP 1.0 functional description single device data/modem data pump 1.2 technical specifications d96v24dsa 1-7 1.2.7.1 power and environmental requirements the power requirements are specified in table 1-4. the environmental specifications are listed in table 1-5. table 1-4. modem power requirements voltage mode current (typ) @ 25c current (max) @ 0c 5vdc 5% operating 60 ma 90 ma sleep 3 ma 4.5 ma note: input voltage ripple 0.1 volts peak-to-peak. the amplitude of any frequency between 20 khz and 150 khz must be less than 500 microvolts peak. table 1-5. modem environmental specifications parameter specification temperature operating 0o c to 70o c (32o f to 158o f) storage -40o c to 80o c (-40o f to 176o f) relative humidity up to 90% noncondensing, or a wet bulb temperature up to 35o c, whichever is less. altitude -200 feet to +10,000 feet
1.0 functional description RC96V24DP 1.2 technical specifications single device data/modem data pump 1-8 d96v24dsa
2-1 d96v24dsa 2.0 2.0 hardware interface the modem functional hardware interface signals are shown in figure 2-1. in this diagram, any point that is active low is represented by a small circle at the signal point. edge triggered inputs are denoted by a small triangle (e.g., tdclk). open- collector (open-source or open-drain) outputs are denoted by a small half-circle (e.g., irq ). active low signals are overscored (e.g., por ). a dock intended to activate logic on its rising edge (low-to-high transition) is called active low (e.g., rdclk ), while a clock intended to activate logic on its falling edge (high-to-low transition) is called active high (e.g., tdclk). when a clock input is associated with a small circle, the input activates on a falling edge. if no circle is shown, the input activates on a rising edge. the modem pin assignments are shown in figure 2-2. the pin assignments are listed by pin number in table 2-1. the hardware interface signal functions are summarized by major interface in table 2-2. the digital and analog interface characteristics are defined in table 2-3 and table 2-4, respectively.
2.0 hardware interface RC96V24DP single device data/modem data pump 2-2 d96v24dsa figure 2-1. rc9623dp functional interface signals RC96V24DP modem device host processor bus interface crystal decoder txd xtlo rxd xtclk tdclk xtli data bus (8) rdclk read write address bus (5) cs +5v reset note: required external components are not shown oscilloscope telephone line interface speaker amplifier (optional) eye pattern generator (optional) eyex eyey eyesync eyeclk txa2 txa1 radvr rbdvr ring spkr +5v rxa d0-d7 rs0-rs4 irq serial interface dgnd agnd
RC96V24DP 2.0 hardware interface single device data/modem data pump d96v24dsa 2-3 figure 2-2. rc9623dp pin signals table 2-1. rc9623dp modem device pin signals pin number signal name i/o type 1rs2ia 2rs1ia 3rs0ia 4 test1 5 sleep oa 6ring 7eyeyob 8eyexob 9 eyesync ob 10 reset id 11 xtli ie 12 xtlo ob 13 +5vd 14 gp18 oa reset xtai xtalp +5vd gp18 gp16 xtclk dgnd1 txd tdclk trsto tstbo tdaco radci ragco modeo rstbo 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 d2 d3 d4 d5 d6 d7 dgnd2 spkr +5va modei tstbi trsti tdaci radco rrsti rstbi nc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 eyesync eyex eyey ring sleep test1 rs0 rs1 rs2 rs3 rs4 read cs write irq d0 d1 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 rrsto rdclk rxd txa2 txa1 rxa rfilo agcin vc nc nc nc rbdvr agnd radvr sleepi radci 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2.0 hardware interface RC96V24DP single device data/modem data pump 2-4 d96v24dsa 15 gp16 oa 16 xtclk ia 17 dgnd1 18 txd ia 19 tdclk oa 20 trsto mi 21 tstbo mi 22 tdaco mi 23 radci mi 24 ragco mi 25 modeo mi 26 rstbo mi 27 rrsto mi 28 rdclk oa 29 rxd oa 30 txa2 o(dd) 31 txa1 o(dd) 32 rxa i(da) 33 rfilo mi 34 agcin mi 35 vc 36 nc 37 nc 38 nc 39 rbdvr od 40 agnd 41 radrv od 42 sleep1 ia 43 ragci mi 44 nc 45 rstbi mi table 2-1. rc9623dp modem device pin signals (continued) pin number signal name i/o type
RC96V24DP 2.0 hardware interface single device data/modem data pump d96v24dsa 2-5 46 rrsti mi 47 radco mi 48 tdaci mi 49 trsti mi 50 tstbi mi 51 mode1 mi 52 +5va 53 spkr o(of) 54 dgnd2 55 d7 ia/ob 56 d6 ia/ob 57 d5 ia/ob 58 d4 ia/ob 59 d3 ia/ob 60 d2 ia/ob 61 d1 ia/ob 62 d0 ia/ob 63 irq oc 64 write ia 65 cs ia 66 read ia 67 rs4 ia 68 rs3 ia notes: (1) mi = modem interconnection (2) nc = no connection (may have internal connection; leave pin disconnected (open). (3) i/o types are described in table 2-3 (digital signals) and table 2-4 (analog signals). table 2-1. rc9623dp modem device pin signals (continued) pin number signal name i/o type
2.0 hardware interface RC96V24DP single device data/modem data pump 2-6 d96v24dsa table 2-2. hardware interface signal definitions label i/o type signal/definition overhead signals xtli ieob crystal/clock ln and crystal out. the dsp must be connected to an external crystal circuit consisting of a 24.00014 mhz crystal and two capacitors. alternatively, xtli, may be driven with a buffered clock (e.g., square wave generator) or a sine wave oscillator. reset id reset. the active low reset input resets the internal modem logic. upon transition of reset from low-to-high, the dsp interface memory bits are set to the default values. +5vd pwr +5v digital supply. +5v 5% is required. +5va pwr +5v analog supply. +5v 5% is required. dgnd gnd digital ground. dgnd gnd analog ground. serial interface five ttl-level hardware interface circuits implement a ccitt v.24-compatible serial data interface with control signals provided through the dsp interface memory. rdclk oa receive data clock. in synchronous mode, the modem outputs a receive data clock (rdclk in the form of 50 1% duty cycle square wave. the low-to-high transitions of this output coincide with the center of received data bits. tdclk oa transmit data clock. in synchronous mode, the modem outputs a transmit data clock (tdclk). the tdclk clock frequency is data rate 0.01% with a duty cycle of 50 1%. xtclk ia external transmit clock. in synchronous mode, an external transmit data clock input (xtclk) can be supplied. rxd oa received data. the modem presents received serial data on the received data (rxd) output and to the interface memory receive data register (rbuffer) in both serial and parallel modes. txd ia transmitted data. the modem obtains serial data to be transmitted on the txd input in serial mode, or from the interface memory transmit data register (tbuffer) in parallel mode. (see tpdm bit.) parallel microprocessor interface address, data, control and interrupt hardware interface signals implement an 8086- compatible parallel microprocessor interface to a host processor. this parallel interface allows the host to change modem configuration, read or write channel and diagnostic data, and supervise modem operation by writing control bits and reading status bits. d0-d7 ia/oa data lines. eight bidirectional data lines (do-d7) provide parallel transfer of data between the host and the modem. cs ia chip select. the active low chip select (cs ) input enables parallel data transfer over the microprocessor bus.
RC96V24DP 2.0 hardware interface single device data/modem data pump d96v24dsa 2-7 rs0-rs4 ia parallel microprocessor interface (cont) register select lines. the five active high register select inputs (rs0 - rs4) address interface memory registers in the modem when cs is low. these lines are typically connected to address lines a0-a4 to address one of 32 8-bit internal interface memory registers (00-1f). the selected register can be read from, or written into, via the 8-bit parallel data bus (do-d7). read write iaia read enable and write enable. reading or writing is controlled by the host pulsing either read or write input low, respectively, during the microprocessor bus access cycle. during a write cycle, data from the data bus is copied into the addressed dsp interlace memory register, with high and low bus levels representing one and zero bit states, respectively. irq oa interrupt request. the irq output structure is an open-drain field-effect-transistor (fet). the irq output can be enabled in the interface memory to allow immediate indication of change of conditions in the modem. the use of irq is optional depending upon modem application. hybrid circuit txa1 txa2 o(df) transmit analog 1 and 2. the txa1 and txa2 outputs are differential outputs 180 degrees out of phase with each other. rxa i(da) receive analog. rxa is a single-ended receive data input from the telephone line interface or an optional external hybrid circuit. vc oa centerpolnt voltage. vc is a +2.5 vdc centerpoint voltage which serves as the internal 'analog ground' reference point. telephone line interface radvr od relay a driver. radvr is an open drain output which can directly drive a relay with greater than 360 q coil resistance and having a 'must operate' voltage of no greater than 4.0 vdc. the radvr output is controlled by the state of the ra bit, except in pulse dial mode. when ra is a 1, the radvr output is active which applies current to the relay coil. in a typical application, radvr is connected to the normally open off-hook relay. in this case, radvr active closes the off-hook relay to connect the modem to the telephone line. rbdvr od relay b driver. rbdvr is an open drain output which can directly drive a relay with greater than 360 q coil resistance and having a 'must operate' voltage of no greater than 4.0 vdc. rbdvr output is controlled by the state of the rb bit. when rb is a 1, the rbdvr output is active which applies current to the relay coil. in a typical application, rbdvr is connected to the normally closed talk/data relay. in this case, rbdvr active opens the relay to disconnect the handset from the telephone line. ring ia ring frequency. a low-going edge on the ring input initiates a ring frequency measurement. a valid ring detection is indicated by the ri bit. table 2-2. hardware interface signal definitions (continued) label i/o type signal/definition
2.0 hardware interface RC96V24DP single device data/modem data pump 2-8 d96v24dsa speaker interface spkr o(df) speaker analog output. the spkr output reflects the received analog input signal. the spkr on/off and three levels of attenuation are controlled by interface memory bits. when the speaker is turned off, the spkr output is clamped to the voltage at the vc pin. the spkr output can drive an impedance as low as 300 ohms. in a typical application, the spkr output is an input to an external lm386 audio power amplifier. sleep mode signals sleep sleep1 oa ia sleep mode output and sleep mode input. sleep output high indicates the dsp is operating in its normal mode. sleep low indicates that the dsp is in the sleep mode. this signal must be connected to the sleep1 input to power down the ia in the sleep mode. sleep can also be used to control power to other devices (e.g., as a speaker enable). diagnostic signals four signals provide the timing and data necessary to create an oscilloscope quadrature eye pattern. the eye pattern is simply a display of the received baseband constellation. by observing this constellation, common line disturbances can usually be identified. eyex, eyey ob eye pattern data x and eye pattern data y. the eyex and eyey outputs provide two serial bit streams containing data for display on the oscilloscope horizontal (x) axis and vertical (y) axis, respectively. this serial digital data can be converted to analog form using two shift registers and two digital-to-analog converters (dacs). eyeclk (rrsto) oa eye pattern clock. eyeclk is a clock for use by the serial-to-parallel converters. the eyeclk output is a 7200/9600 hz clock. eyesync ob eye pattern sync. eyesync is a strobe for word synchronization. the falling edge of eyesync may be used to transfer the 8-bit word from the shift register to a holding register. digital-to-analog conversion can then be performed for driving the x and y inputs of an oscilloscope. modem interconnect rfilo mi receive filter output. rfilo is the output of the internal receive analog filter which must be connected to agcin through a 0.1 f, 20%, dc decoupling capacitor. agcin mi receive agc gain amplifier input. see rfilo. modeo (dsp) modei (ia) mi mode control. serial ia mode control bits. direct modem interconnect line. tdaco (dsp), tdaci (ia) mi transmitter dac signal. transmitter serial digital dac signal. direct modem interconnect line. tstbo (dsp), tstbi (ia) mi transmitter strobe. transmitter 576 khz digital timing reference. direct modem interconnect line. trsto (dsp), trsti (ia) mi transmitter reset. transmitter 7200/9600 hz digital timing reference. direct modem interconnect line. table 2-2. hardware interface signal definitions (continued) label i/o type signal/definition
RC96V24DP 2.0 hardware interface single device data/modem data pump d96v24dsa 2-9 radci (dsp), radco (ia) mi modem interconnect (cont) receiver adc signal. receiver serial digital adc signal. direct modem interconnect line. ragco (dsp), ragci (ia) mi receiver agc signal. receiver serial digital agc signal. direct modem interconnect line. rsrbo (dsp), rsrbi (ia) mi receiver strobe. receiver 576 khz digital timing reference. direct modem interconnect line. rrsto (dsp), rrsti (ia) mi receiver reset. receiver 7200/9600 hz digital timing reference. direct modem interconnect line. table 2-2. hardware interface signal definitions (continued) label i/o type signal/definition table 2-3. digital interface characteristics parameter symbol min. typ. max. units test conditions (1) input high voltage type ia type id v ih 2.0 0.8 (vcc) C C vcc vcc vdc input low voltage v il -0.3 C 0.8 vdc input low current i il C C -400 a vcc = 5.25v output high voltage types oa and ob type od v oh 3.5 C C C C vcc vdc i load = -100 a i load = 0 ma output low voltage types oa and oc type ob type od v ol C C C C C 0.4 0.4 0.75 vdc i load = 1.6 ma i load = 0.8 ma i load = 15 ma threeCstate input current (off) i tsi C C 10 a v in = 0.4 to vcc -1 power dissipation operating sleep p d C C 300 15 450 22.5 mw note: (1) test conditions: vcc = 5v 5%, t a = 0c to 70c (unless otherwise noted).
2.0 hardware interface RC96V24DP single device data/modem data pump 2-10 d96v24dsa table 2-4. analog interface characteristics name type characteristic rxa i (da) 1458 type op amp input txa1, txa2 o (dd) 1458 type op amp output spkr o (df) 1458 type op amp output
3-1 d96v24dsa 3.0 software interface 3.1 interface memory the dsp communicates with the host by means of a dual-port, interface memory the interface memory in the dsp contains thirty-two 8-bit registers, labeled register 00 through 1f. each register can be read from, or written into, by both the host and the dsp. the host communicates with the dsp interface memory via the microprocessor bus. the host can control modem operation by writing control bits to dsp interface memory and writing parameter values to dsp ram through the interface memory. the host can monitor modem operation by reading status bits from dsp interface memory and reading parameter values from dsp ram through interface memory. 3.2 interface memory map a memory map of dsp interface memory identifying the contents of the 32 addressable registers is shown in table 3-1. these 8-bit registers may be read or written during any host read or write cycle. in order to operate on a single bit or group of bits in a register, the host must read a register then mask out unwanted data. when writing a single bit or group of bits in a register, the host must perform a read-modify-write operation. that is, the host must read the entire register, set or reset the necessary bits without altering the other register bits, then write the unaffected and modified bits back into the interface memory register. 3.3 interface memory bit functions table 3-2 summarizes the functions of the individual bits in the interface memory. bits in the interface memory are referred to using the format z:q. the register number is denoted by z (00 through if) and the bit number is located by q (0 through 7, where 0 = lsb).
3.0 software interface RC96V24DP 3.3 interface memory bit functions single device data/modem data pump 3-2 d96v24dsa table 3-1. interface memory map register function register address (hex) bit 7 6 5 4 3 2 1 0 interrupt handling 1f nsia ncia C nsie news ncie C newc 1e tdbia rdbia tdbie C tdbe rdbie C rdbf ram access, control and status 1d xacc C C C iox xcrd xwt xcr 1c x ram address (xadd) 1b yacc C C C C ycrd ywt ycr 1a y ram address (yadd) 19 x ram data msb (xdam) 18 x ram data lsb (xdal) 17 y ram data msb (ydam) 16 y ram data lsb (ydal) C 15 CCCCCCCC C 14 CCCCCCCC control 13 tlvl vol txclk 12 configuration (conf) transmit data buffer 11 CCCCCCCtxp 10 transmit data buffer (tbuffer) status 0f rlsd fed cts dsr ri tm syncd flags 0e rtdet brkd pe fe oe speed 0d C pndet s1det scr1 u1det sadet C C 0c edet C C C dtdig 0b tonea toneb tonec atv25 atbell pnsuc dtdet bel103 0aCCCCCCCcrcs control 09 nv25 cc dtmf org ll data C sleep 08 async tpdm C ddis trfz C rtrn rts 07 rdle rdl l2act C l3act rb ra abort 06 brks exos parsl pen stb wdsz 05 C C C txsq ceqe rceq txvoc C 04 eqres swres C C eqfz ifix agcfz crfz 03 nrzie hdlc split C arc sdis gte C 02 CCCCCCCC receive data buffer 01 CCCCCCCrxp 00 receive data buffer (rbuffer) note: C in the bit columns indicates reserved for modem use only.
RC96V24DP 3.0 software interface single device data/modem data pump 3.3 interface memory bit functions d96v24dsa 3-3 table 3-2. interface memory bit functions mnemonic memory location name/description abort 07:0 hdlc abort . controls sending of continuous mark in hdlc mode. agcfz 04:1 agc freeze . inhibits updating of the receiver agc. arc 03:3 automatic rate change enable . enables automatic on-line rate change sequence. async 08:7 asynchronous/synchronous . selects asynchronous or synchronous data mode. atbell ob:3 bell answer tone detected . reports detection status of 2225 hz answer tone. atv25 ob:4 v25 answer tone detected . reports detection status of 2100 hz answer tone. bel1o3 ob:0 bell 103 mark frequency detected . reports detection status of 1270 hz bell 103 mark. brkd oe:6 break detected . reports receipt status of continuous space. brks 06:7 break sequence . controls sending of continuous space in parallel asynchronous mode. cc 09:6 controlled carrier . selects controlled or constant carrier mode. ceq 05:3 compromise equalizer enable . enables the transmit passband digital compromise equalizer. conf 12:0-7 modem configuration select . selects the modem operating mode. crcs oa:0 crc sending . reports the sending status of the crc (2 bytes) in hdlc mode. crfz 04:0 carrier recovery freeze . disables update of the receivers carrier recovery phase lock loop. cts of:5 clear to send . reports that the training sequence has been completed (see tpdm). data 09:2 data mode . selects idle or data mode. ddis 08:4 descrambler disable . disables the receivers descrambler circuit. dsr of:4 data set ready . reports the data transfer state. dtdet ob:1 dtmf digit detected . reports that a valid dtfm digit has been detected. dtdig 00:0-3 detected dtmf digit . contains the hexadecimal code of the detected dtmf digit. dtmf 09:5 dtmf dial select . selects either dtmf or pulse dialing in the dial mode. edet 00:7 early dtmf detect . reports detection of the high group frequency of the dtmf tone pair. eqfz 04:3 equalizer freeze . inhibits the update of the receivers adaptive equalizer taps. eqres 04:7 equalizer reset . resets the receiver adaptive equalizer taps to zero. exos 06:6 extended overspeed . selects extended overspeed mode in asynchronous mode. fe oe:4 framing error . reports framing error detection or detection of an abort sequence. fed of:6 fast energy detected . reports energy above the turn-on threshold is being detected.
3.0 software interface RC96V24DP 3.3 interface memory bit functions single device data/modem data pump 3-4 d96v24dsa flags of:0 flag sequence . reports transmission status of the flag sequence in hdlc mode, or transmission of a constant mark in parallel asynchronous mode. gte 03:1 guard tone enable . enables transmission of the 1800 hz guard tone (ccitt configuration only). hdlc 03:6 high level data link control . enables hdlc protocol support in parallel data mode. ifix 04:2 eye fix . forces eyex and eyey serial data to be rotated equalizer output. iox 1d:3 i/o register select . specifies that the x ram address (xadd) is an internal i/o register address. l2act 07:5 loop 2 (local digital loopback) activate . selects connection of the receivers digital output internally to the transmitters digital input (locally activated digital loopback). l3act 07:3 loop 3 (local analog loopback) activate . selects connection of the transmitters analog output internally to the receivers analog input (local analog ioopback). ll 09:3 leased line . selects leased line data mode or handshake mode. ncia 1f:6 newc interrupt active . reports that the cause of an interrupt request was completion of a configuration change. (see newc and ncie.) ncie 1f:2 newc interrupt enable . enables the assertion of irq and the setting of the ncia bit. newc i f:0 new configuration . initiates a new configuration; cleared by the modem upon completion of configuration change. this bit can cause irq to be asserted. (see ncie and ncia.) news 1f:3 new status . reports the detection of a change in selected status bits. this bit can cause irq to be asserted. (see nsie and nsia.) nsia 1f:7 news interrupt active . reports that the cause of an interrupt request was a status bit change. (see news and nsie.) nsie 1f:4 news interrupt enable . enables the assertion of irq and the setting of the nsia bit. (see news.) nv25 09:7 disable v.25 answer sequence (data modes), disable echo suppressor tone (fax modes) . disables the transmitting of the 2100 hz cci1t answer tone when a handshake sequence is initiated in a data mode or disables sending of the echo suppressor tone in a fax mode. oe oe:3 overrun error . reports overrun status of the receiver data buffer (rbuffer). org 09:4 originate . selects originate or answer mode. pe oe:5 parity error . reports parity error status or bad crc pnsuc ob:2 pn success . indicates that the receiver has detected the pn portion of the training sequence. ra 07:1 relay a activate . activates the radrv output. parsl 06:4.5 parity select . selects stuff, space, even, or odd parity in the asynchronous parallel data mode. table 3-2. interface memory bit functions (continued) mnemonic memory location name/description
RC96V24DP 3.0 software interface single device data/modem data pump 3.3 interface memory bit functions d96v24dsa 3-5 rb 07:2 relay b activate . activates the rbdvr output. rbuffer 00:0-7 receive data buffer . contains the received byte of data. rdbf 1e:0 receiver data buffer full . reports the status (full or not full) of the receiver data buffer (rbuffer). (see rdbie and rdbia.) rdbia 1e:6 receiver data buffer interrupt active . reports that the cause of an interrupt request is the receiver data buffer (rbuffer) full. (see rdbf and rdbie.) rdbie i e:2 receiver data buffer interrupt enable . enables the assertion of irq and the setting of the rdbia bit when rbuffer is full. (see rdbf and rdbia.) rdl 07:6 remote digital loopback request . initiates a request for the remote modem to go into digital loop-back. rdle 07:7 remote digital loopback response enable . enables the modem to respond to the remote modems digital loopback request. pen 06:3 parity enable . enables generation/checking of parity in asynchronous parallel data mode. rceq 05:2 receiver compromise equalizer enable . controls insertion of the receive passband digital compromise equalizer into the receive path. ri 0f:3 ring indicator . reports detection status of a valid ringing signal. rtdet 0e:7 retrain detected . reports detection status of a retrain request sequence. rtrn 08:1 retrain . controls sending of the retrain request or automatic rate change to the remote modem. rts 08:0 request to send . requests the transmitter to send data. rlsd 0f:7 received line signal detector . reports detection status of the carrier and the receipt of valid data. rxp 01:0 received parity bit . this bit is the received parity bit (or ninth data bit). s1det 00:5 s1 sequence detected . reports detection status of the s1 sequence. sadet 00:2 scrambled alternating ones sequence detected . reports detection status of the scrambled alternating ones sequence. scr1 00:4 scrambled ones sequence detected . reports detection status of scrambled ones sequence. sdis 03:2 scrambler disable . disables the transmitter scrambler. sleep 09:0 sleep mode . controls entry into the sleep mode. the modem requires a pulse on the reset pin to return to normal operation. speed 0e:0-2 speed indication . reports the data rate at the completion of a connection. split 03:5 extended overspeed tx/rx split . limits transmit data to the basic overspeed rate. stb 06:2 stop bit number . selects the number of stop bits in asynchronous mode. swres 04:6 software reset . causes the modem to reinitialize to its power turn-on state. table 3-2. interface memory bit functions (continued) mnemonic memory location name/description
3.0 software interface RC96V24DP 3.3 interface memory bit functions single device data/modem data pump 3-6 d96v24dsa tbuffer 10:0-7 transmitter data buffer . contains the byte to be transmitted in the parallel mode. tdbe 1e:3 transmitter data buffer empty . reports the status (empty or not empty) of the transmit data buffer (tbuffer). (see tdbie and tdbia.) tdbia 1e:7 transmitter data buffer interrupt active . reports that the cause of an interrupt request is the transmit data buffer (tbuffer) empty. (see tdbe and tdbie.) tdbie 1e:5 transmitter data buffer interrupt enable . enables assertion of irq and the setting of the tdbia bit when the tbuffer is empty. (see tdbe and tdbia.) tlvl 13:4-7 transmit level attenuation select . selects the transmitter analog output level attenuation in 1 db steps. the host can fine tune the transmit level to a value lying within a 1 db step in dsp ram. tm 0f:2 te st mod e . reports active status of the selected test mode. tonea 0b:7 tone filter a energy detected . reports status of energy above the threshold detection by the call progress monitor filter in the dial configuration or 1300 hz fsk tone energy detection by the tone a bandpass filter in the tone detector configuration. toneb ob:6 tone filter b energy detected . reports status of 390 hz fsk tone energy detection by the tone b bandpass filter in the tone detector configuration. tonec 05:5 tone filter c energy detected . reports status of 1650 hz or 980 hz (selected by the org bit) fsk tone energy detection by the tone c bandpass filter in the tone detector configuration. tpdm 08:6 transmitter parallel data mode . selects transmitter parallel or serial mode. trfz 08:3 timing recovery freeze . inhibits the update of the receivers timing recovery algorithm. txclk 13:0,1 transmit clock select . selects the transmitter data clock (internal, disable, slave, or external). txp 11:0 transmit parity bit (or 9th data bit) . this bit is the stuffed parity bit (or ninth data bit) for transmission. txsq 05:4 transmitter squelch . disables transmission of energy. txvoc 05:1 tr a nsm i t vo ic e . enables the sending of voice samples. u1det od:3 unscrambled ones detected . reports detection status of the unscrambled ones sequence. wdsz 06:0,1 data word size . selects the number of data bits per character in asynchronous mode (5, 6, 7. or 8). vol 13:2-3 volume control . two-bit encoded speaker volume selects volume off or one of three volume on levels. xacc 1d:7 x ram access enable . controls dsp access of the x ram associated with the address in xadd and the xcr bit. xwt determines it a read or write is performed. xadd 1c:0-7 x ram address . contains the x ram address used to access the dsps x data ram or x coefficient ram (selected by xcr) via the x ram data lsb and msb registers. table 3-2. interface memory bit functions (continued) mnemonic memory location name/description
RC96V24DP 3.0 software interface single device data/modem data pump 3.4 dsp ram access d96v24dsa 3-7 3.4 dsp ram access the dsp contains four sections of 16-bit wide random access memory (ram). because the dsp is optimized for performing complex arithmetic, the ram is organized into real (x ram) and imaginary (y ram) sections, as well as data and coefficient sections. the host processor can access (read or write) the x ram only, the y ram only, or both the x ram and the y ram simultaneously in either the data or coefficient section. xcr 1d:0 x coefficient ram select . controls xadd access to the dsps x coefficient ram or the x data ram. xcrd 1d:2 x ram continuous read . enables read of x ram every sample from the location addressed by xadd independent of the xacc and xwt bits. xdal 18:0-7 x ram data lsb . the least significant byte of the 16-bit x ram data word used in reading or writing x ram locations in the dsr xdam 19:0-7 x ram data msb . the most significant byte of the 16-bit x ram data word used in reading or writing x ram locations in the dsr xwt 1d:1 x ram write . controls the reading of data from, or the writing of data to, the x ram data registers (18 and 19) using the x ram location addressed by xadd and xcr. yacc 1b:7 y ram access enable . controls dsp access of the y ram associated with the address in yadd and the ycr bit. ywt determines if a read or write is performed. yadd 1a0-7 y ram address . contains the y ram address used to access the dsps v data ram or v coefficient ram (selected by ycr) via the y ram data lsb and msb registers. ycr 15:0 y coefficient ram select . controls yadd access to the dsps y coefficient ram or the y data ram. ycrd 15:2 y ram continuous read . enables read of y ram every sample from the location addressed by yadd independent of the yacc and ywt bits. ydal 16:0-7 y ram data lsb . the least significant byte of the 16-bit y ram data word used in reading or writing y ram locations in the dsp ydam 17:0-7 y ram data msb . the most significant byte of the 16-bit y ram data word used in reading or writing y ram locations in the dsp. ywt 1b:1 y ram write . controls the reading of data from, or the writing of data to. the y ram data registers (16 and 17) using the y ram location addressed by yadd and ycr. table 3-2. interface memory bit functions (continued) mnemonic memory location name/description
3.0 software interface RC96V24DP 3.5 interface memory access to dsp ram single device data/modem data pump 3-8 d96v24dsa 3.5 interface memory access to dsp ram the dsp interface memory acts as an intermediary during host to dsp ram or dsp ram to host data exchanges. the addresses stored in modem interface memory ram address registers (i. e., xadd and yadd) by the host, in conjunction with the data or coefficient ram bits (i. e., xcr and ycr) determine the dsp ram addresses for data access. 3.6 host programmable data the parameters available in dsp ram are listed in table 3-3 along with the x ram or y ram address and corresponding xcr or ycr bit value. the scaling for the host programmable data is described in the modem designers guide. table 3-3. dsp ram parameters no. xcr/ycr (1) x ram addr y ram addr parameter 1 1 0-1e adaptive equalizer coefficients, real 1 0 C first coefficient, real (1) (data/fax) 1 10 C last coefficient, real (17) (data) 1 1e C last coefficient, real (31) (fax) 2 1 0-1e adaptive equalizer coefficients, imag. 1 C 0 first coefficient, imag. (1) (data/fax) 1 C 10 last coefficient, imag. (17) (data) 1 C 1e last coefficient, imag. (31) (fax) 3 0 49 C rotated error, real 4 0 C 49 rotated error, imaginary 503fCmax agc gain word 6 0 71 C pulse dial interdigit time 7 0 7c C tone dial interdigit time 8 0 72 C pulse dial relay make time 9 0 7d C pulse dial relay break time 10 0 7e C dtmf duration
RC96V24DP 3.0 software interface single device data/modem data pump 3.6 host programmable data d96v24dsa 3-9 11 0 6c C tone 1 angle increment per sample (txdphi1) 12 0 6d C tone 2 angle increment per sample (txdphi2) 13 0 6e C tone 1 amplitude (txamp1) 14 0 6f C tone 2 amplitude (txamp2) 15 0 73 C max samples per ring frequency period (rdmaxp) 16 0 74 C min samples per ring frequency period (rdminp) 17 0 5e C real part of error 18 0 C 5e imaginary part of error 19 0 C 3d rotation angle for carrier recovery 20 0 59 C rotated equalizer output, real 21 0 C 59 rotated equalizer output, imaginary 22 0 3c C lower part of phase error 23 0 C 3c upper part of phase error 24 1 3f C upper part of agc gain word 25 1 3e C lower part of agc gain word 26 1 2e C average power 27 1 2d C phase error 28 1 2f C tone power (tonea) 29 1 30 C tone power (atbell, bel103, or toneb) 30 1 31 C tone power (tonec, atv25) 31 1 36 C tone detect threshold for tonea (thda) 32 1 37 C tone detect threshold for atbell, bel103, or toneb (thdb) 33 1 38 C tone detect threshold for tonec or atv25 (thdc) table 3-3. dsp ram parameters (continued) no. xcr/ycr (1) x ram addr y ram addr parameter
3.0 software interface RC96V24DP 3.7 modem interface circuit single device data/modem data pump 3-10 d96v24dsa 3.7 modem interface circuit the recommended modem interface circuit is shown in figure 3-1. 34 1C6c biquad 1 coefficient a 0 1C6d biquad 1 coefficient a 1 1C6e biquad 1 coefficient a 2 1C6f biquad 1 coefficient b 1 1C70 biquad 1 coefficient b 2 1 C 71-75 biquad 2 coefficients a 0 C b 2 1C76-7a biquad 3 coefficients a 0 C b 2 1 C 7b-7f biquad 4 coefficients a 0 C b 2 1 C 62-66 biquad 5 coefficients a 0 C b 2 1C67-6b biquad 6 coefficients a 0 C b 2 35 0 32 C turn-on threshold 36 1 79 C turn-off threshold 37 1 C 21 rlsd turn-off time 38 0 70 C transmit level output attenuation 39 1 52 C eye quality monitor (eqm) note: (1)xcr if an xram address is listed; ycr if a yram address is listed. table 3-3. dsp ram parameters (continued) no. xcr/ycr (1) x ram addr y ram addr parameter
RC96V24DP 3.0 software interface single device data/modem data pump 3.7 modem interface circuit d96v24dsa 3-11 figure 3-1. typical modem interface circuit decoupling caps to daa interface radvr* txa2 reset* d0 d1 d2 d3 d4 d5 d6 d7 txa1 rxa read* cs* rs3 rs4 write* rs2 rs1 rs0 xtclk txd tdclk rdclk* rxd irq* eyeclk eyex eyey eyesync reset* ring* vcc vcc vcc vcc c5 2200 pf c10 .1 c11 .1 c13 10 16v l1 47 c7 56pf 5% c17 56pf 5% c14 .1 + - u6 lm386 2 3 5 6 1 4 8 7 c15 .1 c8 .1 c9 12 10% 20v c21 .1 r13 180k r12 100 c16 220 16v c18 1000 pf c12 .1 y1 16.000312mhz 1 2 3 ls1 161201 u7 rc96v24 13 27 46 9 8 7 61 60 59 58 57 18 63 62 67 68 1 2 3 19 16 64 66 65 28 29 10 17 54 40 52 22 48 25 51 20 49 12 11 26 45 21 50 47 23 24 43 39 41 32 31 30 35 6 37 34 33 5 42 53 36 38 44 15 4 14 56 55 vcc rrsto rrsti eyesync eyex eyey d1 d2 d3 d4 d5 txd irq* d0 rs4 rs3 rs2 rs1 rs0 tdclk xtclk write* read* cs* rdclk* rxd reset* dgnd1 dgnd2 agnd vaa tdaco tdaci modeo modei trsto trsti xtlo xtli rstbo rstbi tstbo tstbi radco radci ragco ragci rbvdr* radvr rxa txa1 txa2 vc ring* nc agcin rfilo sleep* sleepi* spkr nc nc nc gp16 test* gp18 d6 d7 c8 .1 c18 .1 uf figure 3-2. typical daa interface circuit radvr* txa1 ring* rxa txa2 vcc vcc r1 18 1w rv1 v150la2 top j4 telco4/6 1 2 3 4 5 6 8 7 r2 7.5k 1w d1 1n970b d2 1n970b line t1 ttc143 k1 relay 1 4 2 3 d5 1n749a r3 100k r6 536 1% d4 1n749a c20 .1 u1 4n35 6 4 5 1 3 2 d3 1n4148 r10 18 c2 .001 10% 1kv c3 .47 10% 250v c1 .001 10% 1kv top j3 telco4/6 1 2 3 4 5 6 8 7 c4 .022uf
3.0 software interface RC96V24DP 3.7 modem interface circuit single device data/modem data pump 3-12 d96v24dsa

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